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Commit fb72c9ce authored by Xin Zhao's avatar Xin Zhao Committed by Pavan Balaji
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Delete CVAR and code that control the batch issuing of RMA operations. 



Since it does not help on performance.
Signed-off-by: Pavan Balaji's avatarPavan Balaji <balaji@anl.gov>
parent 3fdf2c07
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Showing with 0 additions and 123 deletions
src/mpid/ch3/include/mpid_rma_oplist.h
View file @ fb72c9ce
......@@ -142,7 +142,6 @@ static inline MPIDI_RMA_Target_t *MPIDI_CH3I_Win_target_alloc(MPID_Win * win_ptr
e->access_state = MPIDI_RMA_NONE;
e->lock_type = MPID_LOCK_NONE;
e->lock_mode = 0;
e->accumulated_ops_cnt = 0;
e->win_complete_flag = 0;
e->put_acc_issued = 0;
......@@ -302,10 +301,6 @@ static inline int MPIDI_CH3I_Win_enqueue_op(MPID_Win * win_ptr, MPIDI_RMA_Op_t *
if (target->next_op_to_issue == NULL)
target->next_op_to_issue = op;
/* Increment the counter for accumulated posted operations */
target->accumulated_ops_cnt++;
win_ptr->accumulated_ops_cnt++;
fn_exit:
return mpi_errno;
fn_fail:
......
src/mpid/ch3/include/mpid_rma_types.h
View file @ fb72c9ce
......@@ -92,7 +92,6 @@ typedef struct MPIDI_RMA_Target {
enum MPIDI_RMA_states access_state;
int lock_type; /* NONE, SHARED, EXCLUSIVE */
int lock_mode; /* e.g., MODE_NO_CHECK */
int accumulated_ops_cnt;
int win_complete_flag;
int put_acc_issued; /* indicate if PUT/ACC is issued in this epoch
* after the previous synchronization calls. */
......
src/mpid/ch3/include/mpidpre.h
View file @ fb72c9ce
......@@ -327,9 +327,6 @@ typedef struct MPIDI_Win_basic_info {
enum MPIDI_RMA_states exposure_state; \
} states; \
int non_empty_slots; \
int accumulated_ops_cnt; /* keep track of number of accumulated posted RMA operations \
in current epoch to control when to poke \
progress engine in RMA operation routines. */\
int active_req_cnt; /* keep track of number of active requests in \
current epoch, i.e., number of issued but \
incomplete RMA operations. */ \
......
src/mpid/ch3/src/ch3u_rma_ops.c
View file @ fb72c9ce
......@@ -12,23 +12,6 @@ MPIR_T_PVAR_DOUBLE_TIMER_DECL_EXTERN(RMA, rma_rmaqueue_set);
=== BEGIN_MPI_T_CVAR_INFO_BLOCK ===
cvars:
- name : MPIR_CVAR_CH3_RMA_OP_POKING_PROGRESS
category : CH3
type : int
default : 100
class : none
verbosity : MPI_T_VERBOSITY_USER_BASIC
scope : MPI_T_SCOPE_ALL_EQ
description : >-
Specify the threshold of number of posted operations
when starting poking progress in operation routines.
When the value is negative, runtime never pokes progress
engine in operation routines; when the value is zero,
runtime always pokes progress engine in operation
routines; when the value is larger than zero, runtime
starts to poke progress engine when number of posted
operations reaches that value.
- name : MPIR_CVAR_CH3_RMA_OP_PIGGYBACK_LOCK_DATA_SIZE
category : CH3
type : int
......@@ -205,13 +188,6 @@ int MPIDI_CH3I_Put(const void *origin_addr, int origin_count, MPI_Datatype
if (mpi_errno != MPI_SUCCESS)
MPIU_ERR_POP(mpi_errno);
if (MPIR_CVAR_CH3_RMA_OP_POKING_PROGRESS >= 0 &&
win_ptr->accumulated_ops_cnt >= MPIR_CVAR_CH3_RMA_OP_POKING_PROGRESS) {
mpi_errno = poke_progress_engine();
if (mpi_errno != MPI_SUCCESS)
MPIU_ERR_POP(mpi_errno);
}
if (MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD >= 0 &&
win_ptr->active_req_cnt >= MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD) {
while (win_ptr->active_req_cnt >= MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD) {
......@@ -383,13 +359,6 @@ int MPIDI_CH3I_Get(void *origin_addr, int origin_count, MPI_Datatype
if (mpi_errno != MPI_SUCCESS)
MPIU_ERR_POP(mpi_errno);
if (MPIR_CVAR_CH3_RMA_OP_POKING_PROGRESS >= 0 &&
win_ptr->accumulated_ops_cnt >= MPIR_CVAR_CH3_RMA_OP_POKING_PROGRESS) {
mpi_errno = poke_progress_engine();
if (mpi_errno != MPI_SUCCESS)
MPIU_ERR_POP(mpi_errno);
}
if (MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD >= 0 &&
win_ptr->active_req_cnt >= MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD) {
while (win_ptr->active_req_cnt >= MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD) {
......@@ -603,13 +572,6 @@ int MPIDI_CH3I_Accumulate(const void *origin_addr, int origin_count, MPI_Datatyp
if (mpi_errno != MPI_SUCCESS)
MPIU_ERR_POP(mpi_errno);
if (MPIR_CVAR_CH3_RMA_OP_POKING_PROGRESS >= 0 &&
win_ptr->accumulated_ops_cnt >= MPIR_CVAR_CH3_RMA_OP_POKING_PROGRESS) {
mpi_errno = poke_progress_engine();
if (mpi_errno != MPI_SUCCESS)
MPIU_ERR_POP(mpi_errno);
}
if (MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD >= 0 &&
win_ptr->active_req_cnt >= MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD) {
while (win_ptr->active_req_cnt >= MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD) {
......@@ -864,13 +826,6 @@ int MPIDI_CH3I_Get_accumulate(const void *origin_addr, int origin_count,
if (mpi_errno != MPI_SUCCESS)
MPIU_ERR_POP(mpi_errno);
if (MPIR_CVAR_CH3_RMA_OP_POKING_PROGRESS >= 0 &&
win_ptr->accumulated_ops_cnt >= MPIR_CVAR_CH3_RMA_OP_POKING_PROGRESS) {
mpi_errno = poke_progress_engine();
if (mpi_errno != MPI_SUCCESS)
MPIU_ERR_POP(mpi_errno);
}
if (MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD >= 0 &&
win_ptr->active_req_cnt >= MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD) {
while (win_ptr->active_req_cnt >= MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD) {
......@@ -1123,13 +1078,6 @@ int MPIDI_Compare_and_swap(const void *origin_addr, const void *compare_addr,
if (mpi_errno != MPI_SUCCESS)
MPIU_ERR_POP(mpi_errno);
if (MPIR_CVAR_CH3_RMA_OP_POKING_PROGRESS >= 0 &&
win_ptr->accumulated_ops_cnt >= MPIR_CVAR_CH3_RMA_OP_POKING_PROGRESS) {
mpi_errno = poke_progress_engine();
if (mpi_errno != MPI_SUCCESS)
MPIU_ERR_POP(mpi_errno);
}
if (MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD >= 0 &&
win_ptr->active_req_cnt >= MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD) {
while (win_ptr->active_req_cnt >= MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD) {
......@@ -1277,13 +1225,6 @@ int MPIDI_Fetch_and_op(const void *origin_addr, void *result_addr,
if (mpi_errno != MPI_SUCCESS)
MPIU_ERR_POP(mpi_errno);
if (MPIR_CVAR_CH3_RMA_OP_POKING_PROGRESS >= 0 &&
win_ptr->accumulated_ops_cnt >= MPIR_CVAR_CH3_RMA_OP_POKING_PROGRESS) {
mpi_errno = poke_progress_engine();
if (mpi_errno != MPI_SUCCESS)
MPIU_ERR_POP(mpi_errno);
}
if (MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD >= 0 &&
win_ptr->active_req_cnt >= MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD) {
while (win_ptr->active_req_cnt >= MPIR_CVAR_CH3_RMA_ACTIVE_REQ_THRESHOLD) {
......
src/mpid/ch3/src/ch3u_rma_sync.c
View file @ fb72c9ce
......@@ -532,15 +532,6 @@ int MPIDI_Win_fence(int assert, MPID_Win * win_ptr)
/* Make sure that all targets are freed. */
MPIU_Assert(win_ptr->non_empty_slots == 0);
if (assert & MPI_MODE_NOPRECEDE) {
/* BEGINNING synchronization: the following counter should be zero. */
MPIU_Assert(win_ptr->accumulated_ops_cnt == 0);
}
else {
/* ENDING synchronization: correctly decrement the following counter. */
win_ptr->accumulated_ops_cnt = 0;
}
MPIU_Assert(win_ptr->active_req_cnt == 0);
/* Ensure ordering of load/store operations. */
......@@ -764,9 +755,6 @@ int MPIDI_Win_start(MPID_Group * group_ptr, int assert, MPID_Win * win_ptr)
win_ptr->states.access_state = MPIDI_RMA_PSCW_ISSUED;
MPIDI_CH3I_num_active_issued_win++;
/* BEGINNING synchronization: the following counter should be zero. */
MPIU_Assert(win_ptr->accumulated_ops_cnt == 0);
MPIU_Assert(win_ptr->active_req_cnt == 0);
/* Ensure ordering of load/store operations. */
......@@ -884,9 +872,6 @@ int MPIDI_Win_complete(MPID_Win * win_ptr)
/* Make sure that all targets are freed. */
MPIU_Assert(win_ptr->non_empty_slots == 0);
/* ENDING synchronization: correctly decrement the following counter. */
win_ptr->accumulated_ops_cnt = 0;
MPIU_Assert(win_ptr->active_req_cnt == 0);
fn_exit:
......@@ -1074,11 +1059,6 @@ int MPIDI_Win_lock(int lock_type, int dest, int assert, MPID_Win * win_ptr)
}
finish_lock:
if (win_ptr->lock_epoch_count == 1) {
/* BEGINNING synchronization: the following counter should be zero. */
MPIU_Assert(win_ptr->accumulated_ops_cnt == 0);
}
/* Ensure ordering of load/store operations. */
if (win_ptr->shm_allocated == TRUE) {
OPA_read_write_barrier();
......@@ -1182,12 +1162,6 @@ int MPIDI_Win_unlock(int dest, MPID_Win * win_ptr)
}
if (target != NULL) {
/* ENDING synchronization: correctly decrement the following counter. */
win_ptr->accumulated_ops_cnt -= target->accumulated_ops_cnt;
if (win_ptr->lock_epoch_count == 0) {
MPIU_Assert(win_ptr->accumulated_ops_cnt == 0);
}
/* Cleanup the target. */
mpi_errno = MPIDI_CH3I_Win_target_dequeue_and_free(win_ptr, target);
if (mpi_errno != MPI_SUCCESS)
......@@ -1289,12 +1263,6 @@ int MPIDI_Win_flush(int dest, MPID_Win * win_ptr)
MPIU_ERR_POP(mpi_errno);
}
if (target != NULL) {
/* ENDING synchronization: correctly decrement the following counters. */
win_ptr->accumulated_ops_cnt -= target->accumulated_ops_cnt;
target->accumulated_ops_cnt = 0;
}
fn_exit:
MPIDI_RMA_FUNC_EXIT(MPID_STATE_MPIDI_WIN_FLUSH);
return mpi_errno;
......@@ -1388,10 +1356,6 @@ int MPIDI_Win_flush_local(int dest, MPID_Win * win_ptr)
if (target != NULL) {
/* reset upgrade_flush_local flag in target to 0 */
target->sync.upgrade_flush_local = 0;
/* ENDING synchronization: correctly decrement the following counters. */
win_ptr->accumulated_ops_cnt -= target->accumulated_ops_cnt;
target->accumulated_ops_cnt = 0;
}
fn_exit:
......@@ -1470,9 +1434,6 @@ int MPIDI_Win_lock_all(int assert, MPID_Win * win_ptr)
}
finish_lock_all:
/* BEGINNING synchronization: the following counter should be zero. */
MPIU_Assert(win_ptr->accumulated_ops_cnt == 0);
MPIU_Assert(win_ptr->active_req_cnt == 0);
/* Ensure ordering of load/store operations. */
......@@ -1624,9 +1585,6 @@ int MPIDI_Win_unlock_all(MPID_Win * win_ptr)
/* Make sure that all targets are freed. */
MPIU_Assert(win_ptr->non_empty_slots == 0);
/* ENDING synchronization: correctly decrement the following counter. */
win_ptr->accumulated_ops_cnt = 0;
MPIU_Assert(win_ptr->active_req_cnt == 0);
fn_exit:
......@@ -1672,9 +1630,6 @@ int MPIDI_Win_flush_all(MPID_Win * win_ptr)
curr_target->sync.sync_flag = MPIDI_RMA_SYNC_FLUSH;
}
/* ENDING synchronization: correctly decrement the following counters. */
curr_target->accumulated_ops_cnt = 0;
curr_target = curr_target->next;
}
}
......@@ -1697,9 +1652,6 @@ int MPIDI_Win_flush_all(MPID_Win * win_ptr)
} while (!remote_completed);
finish_flush_all:
/* ENDING synchronization: correctly decrement the following counter. */
win_ptr->accumulated_ops_cnt = 0;
MPIU_Assert(win_ptr->active_req_cnt == 0);
fn_exit:
......@@ -1756,9 +1708,6 @@ int MPIDI_Win_flush_local_all(MPID_Win * win_ptr)
enable_flush_local_cnt++;
}
/* ENDING synchronization: correctly decrement the following counters. */
curr_target->accumulated_ops_cnt = 0;
curr_target = curr_target->next;
}
}
......@@ -1816,9 +1765,6 @@ int MPIDI_Win_flush_local_all(MPID_Win * win_ptr)
}
}
/* ENDING synchronization: correctly decrement the following counter. */
win_ptr->accumulated_ops_cnt = 0;
fn_exit:
MPIDI_RMA_FUNC_EXIT(MPID_STATE_MPIDI_WIN_FLUSH_LOCAL_ALL);
return mpi_errno;
......
src/mpid/ch3/src/mpid_rma.c
View file @ fb72c9ce
......@@ -315,7 +315,6 @@ static int win_init(MPI_Aint size, int disp_unit, int create_flavor, int model,
(*win_ptr)->states.access_state = MPIDI_RMA_NONE;
(*win_ptr)->states.exposure_state = MPIDI_RMA_NONE;
(*win_ptr)->non_empty_slots = 0;
(*win_ptr)->accumulated_ops_cnt = 0;
(*win_ptr)->active_req_cnt = 0;
(*win_ptr)->fence_sync_req = MPI_REQUEST_NULL;
(*win_ptr)->start_req = NULL;
......
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