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Rob Latham
MPICH-BlueGene
Commits
1beada6b
Commit
1beada6b
authored
Nov 17, 2014
by
Kenneth Raffenetti
Browse files
use 0 to indicate false in while expression
parent
e9a24700
Changes
1
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Side-by-side
src/mpid/ch3/src/ch3u_recvq.c
View file @
1beada6b
...
...
@@ -595,7 +595,7 @@ MPID_Request * MPIDI_CH3U_Recvq_FDU_or_AEP(int source, int tag,
prev_rreq
=
rreq
;
rreq
=
rreq
->
dev
.
next
;
}
while
(
rreq
);
}
while
(
false
);
}
while
(
0
);
}
}
MPIR_T_PVAR_TIMER_END
(
RECVQ
,
time_matching_unexpectedq
);
...
...
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