Commit c4941656 authored by Sudheer Chunduri's avatar Sudheer Chunduri
Browse files

APMPI module updates

parent 54fe59d5
......@@ -4,14 +4,14 @@
DARSHAN_STATIC_MOD_OBJS += lib/darshan-apmpi.o
DARSHAN_DYNAMIC_MOD_OBJS += lib/darshan-apmpi.po
VPATH += :$(srcdir)/../modules/autoperf/crayxc
VPATH += :$(srcdir)/../modules/autoperf/apmpi
CFLAGS += \
-DDARSHAN_USE_apmpi \
-I$(srcdir)/../modules/autoperf/crayxc
-DDARSHAN_USE_APMPI \
-I$(srcdir)/../modules/autoperf/apmpi
CFLAGS_SHARED += \
-DDARSHAN_USE_apmpi \
-I$(srcdir)/../modules/autoperf/crayxc
-DDARSHAN_USE_APMPI \
-I$(srcdir)/../modules/autoperf/apmpi
lib/darshan-apmpi.o: lib/darshan-apmpi.c lib/darshan-apmpi-utils.h darshan.h darshan-common.h $(DARSHAN_LOG_FORMAT) darshan-apmpi-log-format.h | lib
$(CC) $(CFLAGS) -c $< -o $@
......
......@@ -4,482 +4,95 @@
*
*/
#ifndef __DARSHAN_APXC_LOG_FORMAT_H
#define __DARSHAN_APXC_LOG_FORMAT_H
#ifndef __DARSHAN_APMPI_LOG_FORMAT_H
#define __DARSHAN_APMPI_LOG_FORMAT_H
/* current AutoPerf Cray XC log format version */
#define DARSHAN_APXC_VER 1
/* current AutoPerf MPI log format version */
#define DARSHAN_APMPI_VER 1
#define DARSHAN_APXC_MAGIC ('A'*0x100000000000000+\
'U'*0x1000000000000+\
'T'*0x10000000000+\
'O'*0x100000000+\
#define DARSHAN_APMPI_MAGIC ('A'*0x100000000+\
'P'*0x1000000+\
'E'*0x10000+\
'R'*0x100+\
'F'*0x1)
'M'*0x10000+\
'P'*0x100+\
'I'*0x1)
#define APXC_PERF_COUNTERS \
/* PAPI counters */\
X(AR_RTR_0_0_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_0_0_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_0_0_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_0_0_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_0_0_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_0_0_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_0_0_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_0_0_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_0_0_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_0_1_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_0_1_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_0_1_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_0_1_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_0_1_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_0_1_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_0_1_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_0_1_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_0_1_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_0_2_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_0_2_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_0_2_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_0_2_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_0_2_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_0_2_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_0_2_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_0_2_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_0_2_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_0_3_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_0_3_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_0_3_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_0_3_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_0_3_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_0_3_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_0_3_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_0_3_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_0_3_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_0_4_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_0_4_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_0_4_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_0_4_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_0_4_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_0_4_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_0_4_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_0_4_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_0_4_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_0_5_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_0_5_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_0_5_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_0_5_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_0_5_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_0_5_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_0_5_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_0_5_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_0_5_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_0_6_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_0_6_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_0_6_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_0_6_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_0_6_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_0_6_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_0_6_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_0_6_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_0_6_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_0_7_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_0_7_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_0_7_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_0_7_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_0_7_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_0_7_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_0_7_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_0_7_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_0_7_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_1_0_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_1_0_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_1_0_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_1_0_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_1_0_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_1_0_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_1_0_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_1_0_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_1_0_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_1_1_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_1_1_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_1_1_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_1_1_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_1_1_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_1_1_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_1_1_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_1_1_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_1_1_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_1_2_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_1_2_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_1_2_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_1_2_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_1_2_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_1_2_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_1_2_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_1_2_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_1_2_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_1_3_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_1_3_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_1_3_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_1_3_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_1_3_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_1_3_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_1_3_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_1_3_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_1_3_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_1_4_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_1_4_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_1_4_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_1_4_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_1_4_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_1_4_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_1_4_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_1_4_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_1_4_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_1_5_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_1_5_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_1_5_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_1_5_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_1_5_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_1_5_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_1_5_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_1_5_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_1_5_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_1_6_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_1_6_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_1_6_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_1_6_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_1_6_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_1_6_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_1_6_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_1_6_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_1_6_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_1_7_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_1_7_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_1_7_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_1_7_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_1_7_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_1_7_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_1_7_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_1_7_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_1_7_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_2_0_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_2_0_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_2_0_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_2_0_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_2_0_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_2_0_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_2_0_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_2_0_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_2_0_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_2_1_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_2_1_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_2_1_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_2_1_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_2_1_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_2_1_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_2_1_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_2_1_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_2_1_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_2_2_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_2_2_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_2_2_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_2_2_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_2_2_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_2_2_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_2_2_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_2_2_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_2_2_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_2_3_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_2_3_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_2_3_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_2_3_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_2_3_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_2_3_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_2_3_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_2_3_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_2_3_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_2_4_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_2_4_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_2_4_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_2_4_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_2_4_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_2_4_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_2_4_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_2_4_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_2_4_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_2_5_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_2_5_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_2_5_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_2_5_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_2_5_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_2_5_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_2_5_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_2_5_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_2_5_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_2_6_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_2_6_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_2_6_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_2_6_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_2_6_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_2_6_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_2_6_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_2_6_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_2_6_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_2_7_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_2_7_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_2_7_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_2_7_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_2_7_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_2_7_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_2_7_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_2_7_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_2_7_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_3_0_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_3_0_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_3_0_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_3_0_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_3_0_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_3_0_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_3_0_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_3_0_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_3_0_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_3_1_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_3_1_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_3_1_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_3_1_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_3_1_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_3_1_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_3_1_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_3_1_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_3_1_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_3_2_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_3_2_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_3_2_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_3_2_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_3_2_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_3_2_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_3_2_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_3_2_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_3_2_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_3_3_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_3_3_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_3_3_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_3_3_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_3_3_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_3_3_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_3_3_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_3_3_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_3_3_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_3_4_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_3_4_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_3_4_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_3_4_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_3_4_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_3_4_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_3_4_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_3_4_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_3_4_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_3_5_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_3_5_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_3_5_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_3_5_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_3_5_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_3_5_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_3_5_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_3_5_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_3_5_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_3_6_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_3_6_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_3_6_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_3_6_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_3_6_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_3_6_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_3_6_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_3_6_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_3_6_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_3_7_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_3_7_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_3_7_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_3_7_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_3_7_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_3_7_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_3_7_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_3_7_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_3_7_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_4_0_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_4_0_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_4_0_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_4_0_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_4_0_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_4_0_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_4_0_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_4_0_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_4_0_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_4_1_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_4_1_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_4_1_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_4_1_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_4_1_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_4_1_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_4_1_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_4_1_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_4_1_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_4_2_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_4_2_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_4_2_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_4_2_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_4_2_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_4_2_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_4_2_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_4_2_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_4_2_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_4_3_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_4_3_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_4_3_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_4_3_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_4_3_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_4_3_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_4_3_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_4_3_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_4_3_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_4_4_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_4_4_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_4_4_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_4_4_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_4_4_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_4_4_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_4_4_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_4_4_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_4_4_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_4_5_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_4_5_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_4_5_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_4_5_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_4_5_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_4_5_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_4_5_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_4_5_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_4_5_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_4_6_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_4_6_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_4_6_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_4_6_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_4_6_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_4_6_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_4_6_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_4_6_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_4_6_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_4_7_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_4_7_INQ_PRF_INCOMING_FLIT_VC1) \
X(AR_RTR_4_7_INQ_PRF_INCOMING_FLIT_VC2) \
X(AR_RTR_4_7_INQ_PRF_INCOMING_FLIT_VC3) \
X(AR_RTR_4_7_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_4_7_INQ_PRF_INCOMING_FLIT_VC5) \
X(AR_RTR_4_7_INQ_PRF_INCOMING_FLIT_VC6) \
X(AR_RTR_4_7_INQ_PRF_INCOMING_FLIT_VC7) \
X(AR_RTR_4_7_INQ_PRF_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_0_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_PT_5_0_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_PT_5_0_INQ_PRF_REQ_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_0_INQ_PRF_RSP_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_1_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_PT_5_1_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_PT_5_1_INQ_PRF_REQ_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_1_INQ_PRF_RSP_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_2_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_PT_5_2_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_PT_5_2_INQ_PRF_REQ_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_2_INQ_PRF_RSP_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_3_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_PT_5_3_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_PT_5_3_INQ_PRF_REQ_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_3_INQ_PRF_RSP_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_4_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_PT_5_4_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_PT_5_4_INQ_PRF_REQ_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_4_INQ_PRF_RSP_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_5_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_PT_5_5_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_PT_5_5_INQ_PRF_REQ_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_5_INQ_PRF_RSP_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_6_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_PT_5_6_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_PT_5_6_INQ_PRF_REQ_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_6_INQ_PRF_RSP_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_7_INQ_PRF_INCOMING_FLIT_VC0) \
X(AR_RTR_PT_5_7_INQ_PRF_INCOMING_FLIT_VC4) \
X(AR_RTR_PT_5_7_INQ_PRF_REQ_ROWBUS_STALL_CNT) \
X(AR_RTR_PT_5_7_INQ_PRF_RSP_ROWBUS_STALL_CNT) \
/* end of counters */\
X(APXC_NUM_INDICES)
/*
X(AMPI_ISEND_COUNT) \
X(AMPI_IRECV_COUNT) \
X(AMPI_BARRIER_COUNT) \
X(AMPI_BCAST_COUNT) \
X(AMPI_REDUCE_COUNT) \
*/
/*
X(AMPI_ALLTOALL_COUNT) \
X(AMPI_ALLTOALLV_COUNT) \
X(AMPI_ALLGATHER_COUNT) \
X(AMPI_ALLGATHERV_COUNT) \
X(AMPI_GATHER_COUNT) \
X(AMPI_GATHERV_COUNT) \
X(AMPI_SCATTER_COUNT) \
X(AMPI_SCATTERV_COUNT) \
X(AMPI_REDUCE_SCATTER_COUNT) \
X(AMPI_SCAN_COUNT) \
X(AMPI_EXSCAN_COUNT) \
*/
#define APMPI_PERF_COUNTERS \
Z(AMPI_SEND) \
Z(AMPI_RECV) \
Z(AMPI_ALLREDUCE) \
X(APMPI_NUM_INDICES)
#define APXC_MEMORY_MODES \
X(MM_UNKNOWN) \
X(MM_FLAT) \
X(MM_EQUAL) \
X(MM_SPLIT) \
X(MM_CACHE) \
X(MM_NUM_INDICES)
#define APMPI_PERF_F_COUNTERS \
Y(AMPI_SEND) \
Y(AMPI_RECV) \
Y(AMPI_ALLREDUCE) \
X(APMPI_F_NUM_INDICES)
#define APXC_CLUSTER_MODES \
X(CM_UNKNOWN) \
X(CM_ALL2ALL) \
X(CM_QUAD) \
X(CM_HEMI) \
X(CM_SNC4) \
X(CM_SNC2) \
X(CM_NUM_INDICIES)
#define Z(a) \
X(a ## _CALL_COUNT), \
X(a ## _MSG_SIZE),
#define X(a) a,
/* integer counters for the "BGQ" example module */
enum darshan_apxc_perf_indices
{
APXC_PERF_COUNTERS
};
#define Y(a) \
X(a ## _TOTAL_TIME),
enum apxc_memory_modes
#define X(a) a
/* integer counters for the "MPI" example module */
enum darshan_apmpi_mpiop_indices
{
APXC_MEMORY_MODES
APMPI_PERF_COUNTERS
};
enum apxc_cluster_modes
/* float counters for the "MPI" example module */
enum darshan_apmpi_f_mpiop_indices
{
APXC_CLUSTER_MODES
APMPI_PERF_F_COUNTERS
};
#undef X
#undef Y
#undef Z
/*
#define X(a) a,
// integer counters for the "MPI" example module
enum darshan_apmpi_perf_indices
{
APMPI_PERF_COUNTERS
};
/* the darshan_apxc_router_record structure encompasses the data/counters
* which would actually be logged to file by Darshan for the AP Cray XC
#undef X
*/
/* the darshan_apmpi_record structure encompasses the data/counters
* which would actually be logged to file by Darshan for the AP MPI
* module. This example implementation logs the following data for each
* record:
* - a darshan_base_record structure, which contains the record id & rank
* - integer I/O counters
* - floating point I/O counters
*/
struct darshan_apxc_perf_record
struct darshan_apmpi_perf_record
{
struct darshan_base_record base_rec;
int group;
int chassis;
int blade;
int node;
int marked;
uint64_t counters[APXC_NUM_INDICES];
uint64_t counters[APMPI_NUM_INDICES];
double fcounters[APMPI_F_NUM_INDICES];
};
struct darshan_apxc_header_record
{
struct darshan_base_record base_rec;
int64_t magic;
int nblades;
int nchassis;
int ngroups;
int memory_mode;
int cluster_mode;
uint64_t appid;
};
#endif /* __DARSHAN_APXC_LOG_FORMAT_H */
#endif /* __DARSHAN_APMPI_LOG_FORMAT_H */
#ifndef __DARSHAN_APXC_UTILS_H__
#define __DARSHAN_APXC_UTILS_H__
#ifndef __DARSHAN_APMPI_UTILS_H__
#define __DARSHAN_APMPI_UTILS_H__
#include <regex.h>
......@@ -33,99 +33,7 @@ static void search_hwinfo(const char * mstr, char *mode)
return;
}
static int get_memory_mode (int node)
{
char memory_mode[64];
char mcdram_str[64];
sprintf(mcdram_str, "mcdram_cfg\\[%d\\]=", node);
search_hwinfo(mcdram_str, memory_mode);
if (strcmp(memory_mode, "flat") == 0)
{
return MM_FLAT;
}
else if (strcmp(memory_mode, "cache") == 0)
{
return MM_CACHE;
}
else if (strcmp(memory_mode, "split") == 0)
{
return MM_SPLIT;
}
else if (strcmp(memory_mode, "equal") == 0)
{
return MM_EQUAL;
}
return MM_UNKNOWN;
}
static int get_cluster_mode (int node)
{
char cluster_mode[64];
char numa_str[64];
sprintf(numa_str, "numa_cfg\\[%d\\]=", node);
search_hwinfo(numa_str, cluster_mode);
if (strcmp(cluster_mode, "a2a") == 0)
{
return CM_ALL2ALL;
}
else if (strcmp(cluster_mode, "quad") == 0)
{
return CM_QUAD;
}
else if (strcmp(cluster_mode, "hemi") == 0)
{
return CM_HEMI;
}
else if (strcmp(cluster_mode, "snc4") == 0)
{
return CM_SNC4;
}